Metal wiring patterns used in integrated circuit devices are frequently formed of copper (Cu) because copper has a relatively low resistivity, particularly compared to metal wiring patterns formed of other materials such as aluminum (Al). These metal wiring patterns are frequently separated from each other by intermetal dielectric layers. In order to reduce the parasitic capacitance between adjacent metal wiring patterns and reduce their RC delay, dielectric layers having relatively low dielectric constant values (i.e., low-K dielectrics) have been used as intermetal dielectric layers.
Damascene processing techniques that utilize low-K dielectrics have been used to define copper wiring patterns on integrated circuit substrates. These techniques frequently include forming a low-K dielectric layer on a first copper wiring pattern and then forming via holes and trenches in the low-K dielectric layer, which expose upper surfaces of the first copper wiring pattern. These via holes and trenches are then filled with a copper wiring layer, which may be formed using an electroplating technique. Planarization techniques such as chemical-mechanical polishing (CMP), may then be used to planarize the copper wiring layer into a plurality of second copper wiring patterns and thereby complete a dual-damascene wiring fabrication process.
An example of a conventional dual-damascene processing technique is illustrated by FIGS. 1A-1D. In FIG. 1A, a first low-K dielectric layer 10 is formed on a substrate (e.g., semiconductor substrate). This first low-K dielectric layer 10 may be patterned to define a trench therein, which is subsequently filled with a lower metal line 12 (e.g., copper line). An etch stop layer 14 and an electrically insulating layer 16 (e.g, silicon dioxide) are formed on the first low-K dielectric layer 10, as illustrated. Thereafter, as illustrated by FIG. 1B, a second low-K dielectric layer 17 is formed on the electrically insulating layer 16. Conventional patterning and etching steps are then performed to define a via hole/trench 18 that extends through the second low-K dielectric layer 17, the electrically insulating layer 16 and the etch stop layer 14, and exposes the lower metal line 12. As illustrated, these patterning and etching steps may result in the formation of a via hole 18 that defines a recess in the lower metal line 12. As will be understood by those skilled in the art, the formation of a recess in the lower metal line 12 and the exposure of this recess to an oxygen containing ambient may result in the formation of an oxide residue (not shown) on the lower metal line 12. This oxide residue may be removed by exposing the lower metal line 12 to a wet cleaning solution containing, for example, diluted HF (DHF). However, this exposure to the wet cleaning solution may also result in the formation of undercut regions 20 within the electrically insulating layer 16, which may react with the cleaning solution.
Referring now to FIG. 1C, a step is performed to deposit a first barrier metal layer in the via hole 18 using a physical vapor deposition (PVD) technique, for example. This first barrier metal layer may be a tantalum nitride layer having a thickness in a range from about 50 Å to about 100 Å. This first barrier metal layer operates as a copper diffusion barrier during subsequent processing steps. Unfortunately, the presence of the undercut regions 20 may preclude the formation of a uniform first barrier metal layer on the sidewall of the via hole 18. A directional etching step may then be performed to remove a portion of the first barrier metal layer from an upper surface of the lower metal line 12 and thereby pattern the first barrier metal layer into sidewall barrier segments 22. This removal of the first barrier metal layer from the lower metal line 12 may operate to decrease the contact resistance between lower metal line 12 and a subsequently formed copper plug.
As will be understood by those skilled in the art, the directional etching of the first barrier metal layer to achieve exposure of the upper surface of the lower metal line 12 may result in the formation of resputtered copper spacers 24 on lower sidewalls of the via hole 18. Because of the presence of the undercut regions 20, which may not be sufficiently protected by the sidewall barrier segments 22, copper atoms from the copper spacers 24 may become incorporated into the second low-K dielectric layer 17. Such penetration of copper into the second low-K dielectric layer 17 may increase leakage currents between adjacent metal lines formed in the second low-K dielectric layer 17. This increase in leakage current may degrade device reliability by increasing time dependent dielectric breakdown (TDDB) within the second low-K dielectric layer 17.
Referring now to FIG. 1D, a second barrier metal layer 26 is then conformally deposited into the via hole 18 using, for example, physical vapor deposition (PVD). This second barrier metal layer 26 may be an adhesion enhancing tantalum layer (Ta) having a thickness in a range from about 40 Å to about 200 Å. A blanket copper seed layer (not shown) may then be deposited on the second barrier metal layer 26 and followed by copper electroplating to fill the via hole 18. Planarization techniques may then be performed to define an upper metal line 28 within the via hole 18.